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EMC Improvement Guidelines
Introduction
High-speed digital Integrated Circuits operate in frequency bands where passive components (PCB, decoupling capacitors, PCB connections, packages, ... ) cannot be considered as ideal - and to the contrary contain, parasitic elements (inductance, resistance, ..). Because their impedances depend on the frequency, the emission levels generated by voltage and current drops may not be compliant to the different EMC standards. It is impossible to predict the compliance of a system. However, it is possible to reduce the risk by implementing rules and design techniques in most applications. This application note gives a brief checklist of major points which can degrade EMC and demonstrates how some basic techniques can help to reduce emission levels and harden the electronic system.
8051 Microcontrollers
Application Note
EMC Definitions
Some basic terms are used in this application note and are explained hereafter: * EMC: Electromagnetic Compatibility, the ability of a product to coexist in its intended
electromagnetic environment without causing or suffering functional degradation or damage.
* EMI: Electromagnetic Interference, a process by which disruptive electromagnetic energy is
transmitted from one electronic device to another via radiated or conducted paths (or both).
* Radiated: Energy transmitted by the air via antenna or loops. * Conducted: Energy transmitted via solid medium like cables, PCB connections,
packages,....
There are three elements in the EMC model to analyze and understand an EMC problem: * A Noise source, a source that generates an electromagnetic perturbation, * A victim, an electronic device that receives a perturbation which causes dysfunctionalities, * A coupling path, a medium that transmits energy from the noise source to the victim.
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Figure 1 shows the topology of an EMC environment. A noise source drives a current i(t). This current flows through the left coupling path (PCB connection for example) and causes voltage drops. This voltage perturbation is transmitted to the victim through the right coupling path and can cause a dysfunctionnality if the level is high enough. Figure 1. Elements of EMC Environment
Coupling paths v(t)
+5V i(t)
Noise Source
Victim
To significantly improve the EMC quality of the design the EMC environment through these elements have to be analyzed.
Basic Checklist to be Compliant with EMC
The basic rules to decrease the conducted and radiated emissions through the powersupply are to: * Reduce the speed of the system: - - * - - - * - - - * Choose the lowest system clock frequency, Adapt the technology to the system constraints. Decrease the surface of the magnetic loops, Maintain the signal trace closed to the ground, Shorten the loops around the oscillator and crystal. Opposite magnetic loops, Choose a package with a VCC and VSS pins close together, Choose a package with several VSS and VCC pins connected in opposite side. Increase the PCB connection widths, Use ground and power planes, Adapt the decoupling capacitors to the working frequency of IC's, Shorten the capacitor connection length, Select the smaller package. Put identical capacitors in parallel to reduce the ESR, Choose COG and NPO dielectric types.
Reduce all the magnetic loops of the Printed Circuit Board:
Cancel H field:
Reduce the parasitic inductance of all devices (PCB traces, package, capacitors,...): - - - - -
*
Reduce the Equivalent Series Resistance (ESR): - -
All theses rules are detailed in the following sections.
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Reduce the Speed of the System
Maintain the System Clock Frequency as low as Possible
A key parameter to improve EMC is to reduce the working frequency of the system. The system clock frequency is defined by evaluating the following guidelines: * * * * the real-time events such as interrupts, serial link,.... the CPU time to process all the tasks attached to these events, the most critical window where the CPU has to process a sequence of real-time events, the clock frequency to achieve this window time.
and then increase the clock frequency by 20 to 30% to have a good margin.
Adapt the Technology to the System Constraints
Another key parameter to reduce EMI is to select the slowest technology of the components used in the system (address latch, memories, buffers,...). The spectral envelope has two cut-off frequencies and is shown on Figure 2. The first one (FC1) depends on the pulse width of the signal and the second (FC2) depends on the sharpness of the transition mainly due to the technology. The slower the technology lower the EMI.
Figure 2. Spectrum of the Trapezoidal Signal for a Fast and Slow Technology E0 TW
E=E0 Tw T -20dB/Decade
Slow Technology Fast Technology
TF TR T
FC1=0.33/Tw FC2=0.33/Tr -40dB/Decade
A timing analysis of the system has to be done to choose the slowest technology of the components to determine the electrical characteristics of such devices. When the maximum operation frequency limit is divided by two, EMI is reduced by 12 dB.
Reduce all the Magnetic Loops of the Printed Circuit Board
Decrease the Magnetic Loop Surface
A current flowing around a loop generates a magnetic field (H) proportional to the area of the loop. The following equations give the mathematical expressions when the observation distance is in the near and far field conditions:
S HnearA m = I x -------------------------- , 3 4xxD
where,
S Hfar A/m = x I x ---------------2 xD
I(A):loop current,S(m):loop surface, (m): observation distance, (m): current wavelength. D
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The near field and far condition is expressed by the following formula: 1 D --- = ----------- 2x This ratio indicates the transition where the emission is in far field or in near field conditions (see Figure 3). The far field condition is a specific distance where the electrical and magnetic fields are coupled and perpendicular. In that condition the ratio E/H is the intrinsic impedance of free space equal to 300. In the near field condition the nature of the fields depends on the connection impedance. For a high impedance (Z >>300 ) the field is electric and magnetic if impedance is low (Z << 300 ). Figure 3. Far and Near Field Conditions Z Near 6000 E/H= 300 20 H field
-----------2
Far Electromagnetic field
E field
D
For example at 3 meters, F = 30 MHz and I = 0.1A, the magnetic field intensity is 19.6dbA for a 1cm surface loop and -13.6dbA when the loop surface is doubled. Reducing the surface by a factor of two leads to decrease H field by a factor of 6dB. This can be achieved by carefully checking the PCB lay-out. The decoupling capacitor acts in this way as well. It supplies locally the fast transient current and reduces the length of the current discharging path. It contributes to reduce the closed contour taken by the current and finally the radiation surface as shown in Figure 4. Figure 4. Decoupling Capacitor Reduces the Magnetic Field and the Loop Surface
i S
H
i S
H
Maintain the Signal Trace To maintain a low parasitic inductance of a signal trace, the distance to the ground has to be maintained short. The parasitic inductance of two parallel conductors carrying uniclose to the Ground
form current in opposite direction consists of self and mutual inductances as shown in Figure 5. This figure depicts the two kinds of parallel conductors which can be found and their electrical equivalent model.
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Figure 5. Structure of a Parasitic Inductance
i i
a)
Ground
b)
d
h
d
h
L1 Mk: Mutual inductance L1 Mk L1: Self inductance
L1-Mk L1-Mk
The total inductance for such topology is equal to:
LT = L1 + L2 - 2 x Mk Mk = k x L1 x L2
where L1 and L2 are the self-inductance of the individual conductors and Mk is the mutual inductance between them. If the VCC and VSS are identical then LT is reduced to:
LT = 2 x ( L1 - Mk )
If the coefficient of magnetic coupling k between the two conductors is unity, the mutual inductance would be equal to the self-inductance of one conductor, since
Mk = L1
and the total inductance of the closed loop would be zero. So to minimize the total inductance of the complete current path, the mutual inductance between the conductors must be maximized. Therefore the two conductors should be placed as close as together as possible to minimize the area between them. Figure 6 and Figure 7 give the mutual inductance for different spacings. Figure 6. Mutual Inductance for l = 10 cm and h = 1.6 mm
i
Mk(nH) l=10 cm h=1.6mm
d
h
2
2xh Mk ( nH ) = 200 x l x ln 1 + --------- d
d(mm)
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For this configuration the formula is applicable only if the direct and return currents are flowing through these two traces. Figure 7 plots different Mk values for some PCB trace dimensions. Figure 7. Mutual Inductance Versus the Length and the Height of PCB Traces
i
Mk(nH) = f(L,H) Thickness and width are neglected
d
h
L + L 2 + H 2 2 2 Mk(nH) = 200 x L x ln -------------------------------- + L + H + H H
h(mm)
If there is no dedicated plane for the power it is recommended to maintain as close as possible the tracks to reduce the surface of loop and the parasitic inductance as shown in Figure 8. Figure 8. The Surface of the VCC and VSS Network has to be Reduced
VCC VSS VCC VSS
Shorten the Loops around Oscillator and Crystal
Figure 9 shows the electrical model of a common oscillator implemented in a microcontroller. At the resonance the fundamental currents i1 and i2 have the same amplitude. In the closed loop mode the oscillator is stabilized in the saturation region of the amplifier that generates some harmonics in HF. So the output loop (X2, C2, and VSS) has to be optimized first and then the input loop (X1, C1 and VSS). In both cases they have to be as small as possible.
Figure 9. Oscillator Lay-out
X1
i0
X2
C2
C1
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C1
C2
i2
i1
X2 X1 Vss
Crystal
EMC Guidelines
Cancel the H Field
Opposite Magnetic Loops
Identical circuits have to be implemented as in Figure 10. In this type of implementation the magnetic loop surface is the same and the H field are generated in opposite side which tends to cancel them. Other implementations can be used but this one needs only one decoupling capacitor for two chips. Figure 10. H Field Cancellation
vcc i1 i2 vcc
vss
vss
A1 A1 x i1 + A2 x i2
A2 =0
Choose a Package with a When a VSS and VCC pins are close together the magnetic coupling can be close to 0.8 and the mutual inductance can reach the self inductance of one pin and cancel magVCC and VSS Close netic field of the total inductance of the VSS and VCC pins. This true when ivss and ivcc Together
have the same magnitude and the same phase which is the case for the current flowing through a digital core of an I.C. but not completely true for an output buffer.
Figure 11. VSS and VCC Pins Close Together Can Cancel the Hfield
VSS VCC ivss ivcc
L1: Self inductance Mk: Mutuel inductance
ivcc ivss
L2 Mk
Mk = k x L1 x L2 LT = L1 + L2 - 2 x Mk
Choose a Package with Several VSS and VCC Pins Connected in Opposite Side
Double the number of VCC and VSS pins reduce by half the equivalent pin inductance and decrease down to 6dB the H field. If the second pin is mounted in the opposite side, the H field can be further reduced by 3 to 4 dB because a part of the H field is cancelled as shown in Figure 12 and reported in Figure 13. Figure 12. Double and Opposite VSS Pins Reduce 3 to 4dB the H Field
ivss/2
H
VSS ivss/2
H
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Figure 13. Double and Opposite VSS Pins Reduce the Radiated Emissions Down to 10dB
Reduce the Inductance of all Devices (PCB traces, package, capacitors,...)
Increase the Width of the Because the real world is not an ideal, a power-supply connection is not a pure short-circuit but a trace with parasitic elements such as resistors and inductors. PCB Connections
Figure 14. PCB Trace Modelization
Z(f) d
PCB Trace width, L=10cm
Resistance(ohm) Inductance(nH)
0.1mm 1mm
0.944 340 0.094 258
1cm
0.009 168
L e: PCB trace thickness in mm, d: PCB trace width mm, L: PCB length in m. e=36m for typical PCB
d=0.1mm d=1mm LT
d=1cm
2xL d+e LT ( H ) = 0, 2 x L x Ln ------------ + 0, 5 + 0, 22 x ------------ d + e L L RT ( m ) = 17 x -----------dxe
RT
F
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This PCB trace is a complex impedance which varies with the frequency. Figure 14 plots the impedance versus the frequency for three different trace widths and for a length and a thickness trace assumed to be 10 cm and 36m respectively. A PCB trace introduces voltage ripples and the width of PCB traces have to be large enough not to introduce a voltage drop which could be to high. For example, when a 0.1A current at 30 MHz flows a PCB trace with 10 cm length and 0.1 mm width, this causes a 0.62V voltage drop. If the width is 100 times the previous one the voltage drop is reduced by a factor of two.
Used Power and Ground Planes
Microstrip Topology The total inductance of a loop (LT) is drastically reduced when using a VSS plane because the equivalent inductance of the plane (LPlane) is much lower than the PCB trace (LTrace) as shown in Figure 15. This is mainly due to the contour taken by the H field which is much larger than the contour taken around the signal trace. These two inductances are rather independent and can be evaluated separately. The ground plane inductance is not affected by the PCB trace width and can be evaluated using the following expression:
LPlane ( nH/cm ) = ---------w
5xh
The PCB trace inductance can be evaluated using the following expression:
LTrace(nH/cm) = 10
-9
2 wt 32 x h x ln 1 + ------------------- x 1 + x ------------ 2 8 x h wt
This inductance is independent of the PCB ground width. For example a trace of 10 cm length and 1mm width and separated from the ground plane by 1.6mm presents an inductance of 51nH. A plane with the same dimensions and 10 cm width presents an inductance of 0.8nH. So the total inductance is the sum of the PCB trace and plane (51nH). The same trace without the ground plane has an inductance equal to 115nH. Thanks to the plane the trace inductance is reduced down to 2.5 factors. Figure 15. A VSS Plane has a Lower Trace Inductance and Reduces the PCB Track Inductance
w
i
L(nh/cm)
w=10 cm , wt=1mm
l Trace inductance Plane inductance wt h LT = LTrace + LPlane
h(mm)
Power and Ground Planes
This is the best solution to reduce the parasitic elements because the parasitic inductance is very small due to a very large contour and a good magnetic coupling factor. It can be modelized by an LC circuit if the largest dimension between the source and the
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load is less than 1 tenth of the minimum wave length. Otherwise the PCB acts as a line or an antenna. Figure 16. VCC and VSS Planes are Equivalent to an LC Model w
S * CPcb ( pF ) = 8, 85 x er x --h
l er=4.8
LPcb
h L(nH) = 5 x x l x --w
LVcc=LVss=L CPcb
h
The PCB capacitor consists in two copper planes with a dielectric inserted between the two planes. The equivalent capacitor (CPcb) is evaluated using the formula in Figure 16. For example a 10 cm by 10 cm plane with 35m thickness and separated by 1.6 mm has a total inductance of 0.05 nH and a capacitor equal to 271 pF. The frequency resonance of the plane is 1.4 GHz. So the power-plane technique is efficient for high frequencies if the distance between the source and the load is short. These plans are not so efficient in low frequency because the equivalent capacitor is not so high and the impedance across the circuit increases and the emission levels too. In low and medium frequency ranges additional decoupling capacitors help to maintain this impedance low. Figure 17. Power-supply Planes Characteristics
LVss(nH/cm)
VCC plane
LVcc(nH/cm)
l=10 cm w=10 cm
l
w
VSS plane
h
LPCB=LVcc+LVss
h(mm)
The next table shows the value of the PCB inductance for the three configurations seen above. The Vcc and Vss Power plane configuration gives the best result and a large decoupling capacitor. Table 1. Comparison of PCB inductance for w = 1mm, wt = 10cm, l = 10cm, h = 1.6mm
Vcc PCB trace Vss PCB trace Inductance(nH) Capacitance(pF) 115 + 115=230 5 pF Vcc PCB trace Vss plane 51 + 0.8=51.8 20 pF Vcc Plane Vss Plane 0.025 + 0.025=0.05 271 pF
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Adapt Decoupling Capacitors to the Working Frequency
A capacitor is not pure and can be modelized like an RLC circuit. The surface mount devices (SMD) have the smallest internal and external inductances and have to be selected to get the best results. Figure 18 shows the equivalent electrical model and plots the frequency response for a SMD 100 nF capacitor. The capacitor acts like a capacitor, a resistor or an inductor but depends on the frequency bands: * * * Medium frequency band: 0 Hz to 6 MHz: the capacitor is a pure capacitor, Resonance frequency: 6-7 MHz: the capacitor is a pure resistance, High frequency: > 7 MHz: the capacitor acts as a pure inductance.
Figure 18. Self-Resonance Frequency of True Capacitor
ESL Capacitor ESL=10nH C C=100nH ESR=0.2oHm
Resistance Inductor
ESR
The frequency behavior depends on the type of capacitor. Table 2 gives the electrical characteristics for different capacitors. Table 2. Capacitor Characteristics Comparison
1 F Tantale R L(nH) Fr(MHz) 0.8 6 2 100 nF Ceramic 0.08 3 7.1 10 nF Ceramic 0.2 3 29
Figure 19 plots the frequency response for different types of capacitors.
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Figure 19. Plots Versus Frequency of Several Types of Capacitors
Z(f)
100nF Ceramic
10nF Ceramic 1F tantale
Assuming the frequency band of the noise is in the range 10MHz to 100MHz and to be compliant the network impedance has to be less than -10dBohms. Figure 20 plots the power network impedance versus the frequency and the impact of the decoupling capacitors on the impedance of the network. Five decoupling capacitors have to be added to be in the -10dBohms specification. Each capacitors is calculated to damp the pic of each frequency resonances. Figure 20. Decoupling Effects on the Network
C=3.3nF F
C=3.3nF + 5.6nF F
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C = 3.3nF + 5.6nF + 10nF
C = 1.8nF + 3.3nF + 5.6nF + 10nF
C = 1nF + 1.8nF + 3.3nF + 5.6nF + 10nF
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Shorten the Capacitor Connection Length
When the capacitor value is assumed to be constant, the resonance frequency depends on the inductance. The total inductance of the circuit consists of the intrinsic capacitor inductance and the inductance of the connections. The higher the inductance, the lower the resonance frequency. It is recommended to maintain as short as possible the length of the connections. Figure 21. Connection Increase the Impedance in H.F Z(f)
No connection
1 cm 5 cm
Figure 21 plots the capacitor impedance versus three different connection lengths. The resonance varies from 7 MHz to 30 MHz when the connection length varies from 0 to 5 cm.
Select the Smallest Package
The package is used to connect the die to the pins but this connection consists of an inductance and a resistance. The die has an internal capacitance and the package in series with the die can be modeled like an RLC circuit which has a resonance frequency. It is recommend to use the smallest package in order to reduce the Q factor. Figure 22 shows the effect on the Q factor for a DIL and PLCC package and the die without the package (COB).
Figure 22. Impedance for a DIL, PLCC and a COB
DIL PLCC
Z(f)
LP
LP DIL PLCC LP COB
LP
Package LP
PLCC 6nH
DIL 20nH
COB 2nH
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Figure 23 compares the radiated emissions between a DIL and PLCC package. Emissions can be reduced down to 7dB in the range 0.15 MHz to 400 MHz using a PLCC package instead of a DIL package. Figure 23. Package Effect on Radiated Emissions
Reduce the Equivalent Series Resistance
Identical Capacitors in Parallel to Reduce the ESR
If the impedance of the power network is out of specification in some frequency bands, several identical capacitors can be connected in parallel to reduce the equivalent ESR. This impedance is reduced by a factor of two each time the number of capacitors is doubled (see Figure 24).
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Figure 24. ESR is Reduced by Connected Several Identical Capacitors in Parallel
1 x 10nF 2 x 10nF 4 x 10nF
Choose COG, NPO and X7R dielectric types
Capacitors that have these dielectrics have the lowest ESR and a good stability in temperature and the value can cover from few pF to several tens of nF.
Conclusion
Most of the EMC improvements detailed in this application note are already known but they are not always applied. There is not a unique solution to improve the EMC of a system but most yield to a cumulative improvement. Designers must keep in mind these mechanisms and apply them early in the conception phase of a system to ensure EMC compliance. * * * * * * Controlling Radiated Emissions by design, Michel Mardiguian, Chapman&Hall Printed Circuit Board Design Techniques for EMC Compliance, MarkI. Montrose, IEEE Press Introduction to Electromagnetic Compatibility, Clayton R.Paul, Wiley Interscience Noise Reduction Techniques In Electronic Systems, Henry W.Ott, Wiley Interscience Computing Inductive noise of Chip Packages, A.J. RAinal, AT&T Bell Laboratories Technical Journal Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS technology, IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 22, NO. 3, AUGUST 1999, Larry D.Smith, Raymond E. Anderson, Douglas W. Forehand, Thomas J. Pelc and Tanmoy Roy, Member, IEEE, High-Speed Digital Design, Howard Jonson & Martin Graham, PTR PH.
References
*
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Atmel Corporation
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